Research team led by the Hitachi Cambridge Laboratory demonstrates an innovative hybrid circuit for quantum computers
Artistic representation of the CMOS hybrid circuit used to perform the experiment:
The chip contains two cells, each composed of one control transistor and one quantum device.
Hitachi Europe today announced that researchers at the Hitachi Cambridge Laboratory, working in collaboration with academic partners at the University of Cambridge, University College London, and CEA-LETI, have developed and demonstrated a hybrid electronic circuit to address a barrier to realizing a practical large-scale quantum computer known as the "I/O problem."
Inspired by dynamic random-access memory (DRAM) architecture, the hybrid electronic circuit combines conventional and quantum devices on a chip using complementary metal-oxide semiconductor (CMOS) technology, to deliver input and output signals to quantum processors while keeping the number of connections manageable, and thereby reduce the complexity of quantum computing architecture. This innovation represents another milestone in current worldwide efforts for the realization of a practical large-scale fault-tolerant quantum computer.