To the body of this page  Hitachi Global Site    Japanese sites of related products Global Site

The site nameHigh Performance Computergo GLOBAL HITACHI Home


Starting of the Global Navigation |  Home  |   about Hitachi  |  Investor  |  Global Network  |Ending of the Global Navigation

    Customer Service    products & services
Search by Google

 > advanced search


Staring of the Bread crumb Home >  HITACHI SR8000 Series Super Technical Server  >  Features Ending of the Bread crumb

The Page Title

HITACHI Super Technical Server SR8000 : Features

 



starting body of the pages
 

Technology that opens the door to a new era of scientific and engineering computation.

 

High performance RISC microprocessor

 
This has been developed by Hitachi and is fabricated by them in leading edge 0.14 micrometer gate length CMOS technology.

It is characterised by :
 (1) 64-bit addressing.
 (2) excellent arithmetic performance and memory throughput.
 (3) high reliability.
 

Pseudo Vector Processing (PVP) facility

 
To maximize the SR8000 Series' microprocessors' efficiency on large scale problems, they have the "pseudo vector processing" facility. This allows data to be fetched from main memory, in a pipelined manner, without stalling the succeeding instructions. The result is that data is fed from memory into the arithmetic units as effectively as in a vector type supercomputer.
 

CO-operative Micro-Processors in single Address Space(COMPAS) feature

 
The SR8000 Series' nodes are formed from multiple RISC microprocessors. These benefit from the "co-operative micro-processors in single address space" feature, which allows the rapid simultaneous start up of all microprocessors in a node. This allows each node to achieve performance comparable to a typical vector processor, while allowing a higher total performance when using them in parallel.
 

Multidimensional crossbar network

 
For effective, scalable, parallel processing, the network that interconnects the nodes is a key technology. As the number of nodes increases, maintaining system performance requires that the network scales in proportion. The SR8000 Series has a "multidimensional crossbar network". This delivers high performance in various communication patterns and scales with increasing number of nodes.
 

Scalable from 32 GFLOPS to 7.3 TFLOPS.

 

SR8000 Series configurations cover a wide performance range.

 
These start with the entry level 32 GFLOPS system, and grow to the high end, 7.3 TFLOPS system, 230 times more powerful. The user can select most suitable configuration according to the computation needs and tasks. The latest air cooling techniques and high density packaging are used throughout. This results in the delivery of some 54 times (in the case of model G1) the performance of Hitachi's vector supercomputers for comparable power consumption and floor footprint.
 

Flexible operation and system configuration for an efficient, open environment.

 

Partitioned operation

 
The SR8000 Series' nodes can be divided into groups or partitions. Each can be used to execute independent codes, allowing flexible configuration to application requirements.
 

Interactive and batch operation

 
The SR8000 Series supports both methods of "Interactive operation" and "Batch operation". Interactive operation is achieved by remote login from workstations or PCs connected over a network, and the starting of jobs directly by command. In batch, the Network Queuing System (NQS) software is used to submit jobs from the workstation or PC to a queue for execution in a partition of the SR8000 Series. In either case, the monitoring of job progress is possible.
 

Flexible network connections

 
Ethernet, Fast Ethernet, Gigabit Ethernet, ATM and HIPPI, all with the TCP/IP protocol, are amongst the networks supported by the SR8000 Series.
 

High reliability

 
This is a vital consideration in any complex system comprising many components.

In the SR8000 Series, a high level is achieved through the use of technologies such as :
   (1) A RISC microprocessor with parity checking in the data & address lines, as well as arithmetic units.
   (2) Memory with Error Correction Code (ECC) capable of correcting burst errors (errors of multiple consecutive bits).
   (3) An inter node network capable of re-transmitting messages when errors are detected.
 
Ending body of the pages


SR11000 Series model K2

SR11000 Series model J1

SR8000 Series

Features

Software

Specifications
ローカル・ナビゲーションここまで

To the top of this Page

 
Starting of the footer  | Term of Use | Privacy Policy | Contact us |Ending of the footer

© Hitachi, Ltd. 1994, 2006. All rights reserved.