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Hitachi Micro Device & Solution

Hitachi

IP Core

IP Core : PHY (PCIe / DDR3)

Support IP/PHY(PCIe DDR3)

Hitachi provides PHY interfaces to realize high-performance LSIs.

With increasingly high LSI performance, the input/output interfaces of LSI circuits and reliability become crucial factors. On the basis of technology gained through the development for IT network equipment, we support PCI Express (with their high general-purpose applicability) and DDR3 SDRAM interfaces.

Features

[ PCI Express Gen1 / Gen2 ]

  • Lane widths ; x 4 (generation 1), x 4 or x 8 (generation 2)
  • Interface between the Media Access Control (MAC) layer and the physical coding sub-layer complies with the PIPE specification
  • Built-in self-test functions

PIPE Interface

Physical Layer

[ DDR3 ]

  • Bit rates can be up to 800 Mbps
  • Built-in self-test functions

Physical Layer

IP Core : SerDes I/O PLL

Support IP(SerDes I/O PLL)
Y:80mV/div, X:50ps/div

Hitachi provides high-speed interfaces to realize high-performance LSIs.

With increasingly high LSI performance, the input/output interfaces of LSI circuits and reliability become crucial factors. On the basis of technology gained through the development of IT network equipment, we provide serdes (serializer-deserializer) macro cells that support various interface standards, along with various kinds of I/O and high-precision PLLs.

Features

[ SerDes ]

  • Built-in self-test functions
  • Consult the list below (standards, bit rates, and lane widths).
Standards Bit Rates Lane Widths
Gigabit Ethernet 1.25Gbps x1, x8
PCI Express Gen1 2.5Gbps x4
XAUI 3.125Gbps x4
PCI Express Gen2 5Gbps x4, x8
XFI 10.3Gbps x4

[ I/O ]

  • Various kinds of I/O to cover the range from low to high (Gbps) rates
  • Built-in self-test functions such as DC parametric tests and AC tests
 
I/O Standards I/O Supply Voltage [V] Comments
LV-CMOS 1.2/1.5/1.8/2.5  
LV-TTL 3.3 PCI,PCI-X
LVDS 2.5  
SSTL 1.5/1.8 DDR3/2
HSTL 1.5  
High Speed CMOS 1.2  
Differential CMOS (CTT Type) 1.2 CTT : Center Terminated Transceiver

[ PLL ]

  • Supporting a wide range of frequencies
  • Built-in self-test functions
  90nm CMOS ASIC
Input Clock Frequency 37.5~300MHz
Output Clock Frequency 150~2400MHz
VCO Frequency 1200~2400MHz
Multiplication Ratio x8~x32

IP Core : High-speed memory (RAM / CAM)

IP Core/High-speed memory(RAM / CAM)

Hitachi realizes high-performance LSIs by providing memory IP cores with high-speed and low-power consumption.

With increasingly high LSI performance, the need for memory IP cores with high-speed and low power consumption has become more pressing. We meet a broad range of needs by optimizing device selection through power-supply options and read-timing options for the sake of higher speeds in terms of cycles and access operation, including circuit technology for higher speeds and lower power consumption.

Features

  • High-density dual-port SRAM macro is realized in the same area as single-port SRAM
  • A high-speed and low-noise ternary CAM macro features reduced peak currents in search operations
  • Supporting a menu of memory types to cover the wide range from high-speed to low-power applications
 
Memory Types Functions Word/Bit Range Power-supply Options Read-timing
Options
1port SRAM 1rw 128~2kw 8~72b High-speed versions
and low-leakage-current versions		 Flow through/
Pipelined
2port SRAM 1r+1w 64~1kw 8~90b
2port SRAM
High Density		 1r+1w 128~32kw 8~72b Flow through
2port
Register File		 1r+1w 4~32w 4~44b High-speed versions
TCAM 1rw
Search		 128~4k
entry		 128~192b Pipelined
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PCI Express(R) is a trademark or registered trademark of PCI-SIG Corporation in the United States and other countries.
*
Ethernet is a product name of Xerox Corporation.
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All other company names and product names in this website are trademarks or registered trademarks of the respective companies.

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