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Hitachi Micro Device & Solution

Hitachi

Business Flow

We prepare the business flow outline for the shuttle and the foundry services as shown in the next figure. We can accommodate it to customer's needs.

Business Flow

Process Design Kit

We provided a process design kit (PDK) which includes a design guide line, device model parameters, CMOS logic cell libraries, DRC/ERC rules, etc.

Process Design Kit
Design Flow EDA Environment PDK and Data
Schematic entry Cadence-DFII(IC5.1.41) Composer, Symbol
Agilent-ADS schematic, Symbol		 Design Guideline
Layout rule, etc.
Circuit
Simulation		 Cadence Spectre,MMSIM
Synopsys Hspice
Agilent ADS		 Device Model Parameter
Layout Cadence Virtuoso-XL Pcell, Cell layout
Phisical
Verification		 Cadence Assura
Mentor Graphic Calibre		 DRC/LVS/ERC rule
Parasitic
Extraction		 Cadence Assura-QRC Extraction DB
  • Our PDK supports various EDA tools mainly made by Cadence design system, Inc.
  • A few kinds of tools are unsupported.
  • PDK might be changed for an improvement.

Delivered IC, etc.

You can choose various configurations of the delivered IC as follows.

  • Back-grinded wafer (Standard in our foundry service.)
  • Front-end process completed wafer, sawn wafer, or bump processed wafer.
  • Sawn die. (Standard in shuttle service)
  • Various packaged IC

We provide the followings as manufacture monitoring data.

  • Device characteristics measured at the end of a front-end process. (Probe test data)
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